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ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 ds100br111 ultra low power 10.3 gbps 2-channel repeater with input equalization and output de-emphasis check for samples: ds100br111 1 features description the ds100br111 is an extremely low power, high 2 ? two channel repeaters for up to 10.3 gbps performance dual-channel repeater for serial links ? ds100br210 : 2x unidirectional channels with data rates up to 10.3 gbps. the ds100br111 ? ds100br111 : 1x bidirectional lane pinout is configured as one bidirectional lane (one transmit, one receive channel). ? 10g-kr bi-directional interface compatibility ? allows for back-channel communication the ds100br111 inputs feature a powerful 4-stage continuous time linear equalizer (ctle) to provide a and training boost of up to +36 db at 5 ghz and open an input ? low 65mw/channel (typical) power eye that is completely closed due to inter-symbol consumption, with option to power down interference (isi) induced by the interconnect unused channels mediums such as an fr-4 backplane or awg-30 ? advanced signal conditioning features cables. the transmitter features a programmable output de-emphasis driver with up to -12 db and ? receive equalization up to +36 db allows amplitude voltage levels to be selected from ? transmit de-emphasis up to -12 db 700 mvp-p to 1200 mvp-p to suit multiple application ? transmit vod control: 700 to 1200 mvp-p scenarios. ? < 0.3 ui of residual dj at 10 gbps when configured as a 10g-kr repeater, the ? programmable via pin selection, eeprom or ds100br111 allows the kr host and the end point to smbus interface optimize the full link by adjusting transmit and receive equalizer coefficients using back-channel ? single supply operation selectable: 2.5v or communication techniques specified by the 802.3ap 3.3v standard. ? flow-thru pinout in 4mmx4mm 24-pin leadless the programmable settings can be applied via pin wqfn package contol, smbus (i2c) protocol or an external ? > 5kv hbm esd rating eeprom. when operating in the eeprom mode, ? industrial -40 to 85 c operating temperature the configuration information is automatically loaded range on power up ? this eliminates the need for an external microprocessor or software driver. applications part of national's powerwise family of energy ? high-speed active copper cable modules and efficient devices, the ds100br111 consumes just 65 mw/channel (typical), and allow the option to turn-off fr-4 backplane in communication systems unused channels. this ultra low power consumption ? 10ge, 10g-kr, fc, sas, sata 3/6 gbps (with eliminates the need for external heat sinks and oob detection), infiniband, cpri, rxaui and simplifies thermal management in active cable many others. applications. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2011 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com typical application block diagram - detail view of channel (1 of 2) 2 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111 in+ in- eq idle detect outbuf smbus vod/ de-emphasis control vdd smbus tx idle enable dem eq[1:0] out+ out- 50 : 50 : vod smbus los channel status and control sd_th tx_dis mode asic/fpga asic/fpga interconnect cable ds100br111 ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 pin diagram (1) the center dap on the package bottom is the device gnd connection. this pad must be connected to gnd through multiple (minimum of 4) vias to ensure optimal electrical and thermal performance. figure 1. ds100br111 pin diagram 24 lead copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: ds100br111 ina+ ina- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los vod_sel / readen# mode / done# sd_th outa+ outa- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 eqb1/ad2 ensmb 1 2 5 63 scl/demb eqb0/ad3 sda/dema 4 vdd tx_dis ad1/eqa1 ad0/eqa0
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com pin descriptions (1) pin name pin number i/o, type pin description differential high speed i/o's ina+, ina- , 24, 23 i, cml inverting and non-inverting cml differential inputs to the equalizer. a on-chip 50 inb+, inb-, 11, 12 termination resistor connects inx+ to vdd and inx- to vdd. outa+, outa-, 7, 8 o,cml inverting and non-inverting 50 driver outputs with de-emphasis. compatible with ac outb+, outb-, 20, 19 coupled cml inputs. control pins ensmb 3 i, lvcmos system management bus (smbus) enable pin float tie high = register access, smbus slave mode float = smbus master read from external eeprom tie low = external pin control mode ensmb = 1 (smbus mode) scl 5 i, lvcmos ensmb master or slave mode o, open smbus clock input pin is enabled. a clock input in slave mode. can also be a clock drain output in master mode. sda 4 i, lvcmos, ensmb master or slave mode o, open the smbus bidirectional sda pin is enabled. data input or open drain (pull-down only) drain output. ad0-ad3 10, 9, 2, 1 i, lvcmos, ensmb master or slave mode float smbus slave address inputs. in smbus mode, these pins are the user set smbus (4-levels) slave address inputs. there are 16 addresses supported by these pins. pins must be tied low or high when used to define the device smbus address. (2) readen# 17 i, lvcmos when using an external eeprom, a transition from high to low starts the load from the external eeprom done# 18 io, eeprom download status lvcmos, high indicates error / still loading float low indicates download complete. no error. (4-levels) ensmb = 0 (pin mode) eqa0, eqa1 10, 9 i, lvcmos, eqa/b ,0/1 control the level of equalization of each channel. the eqa/b pins are eqb0, eqb1 1, 2 float active only when ensmb is de-asserted (low). (4-levels) when ensmb goes high the smbus registers provide independent control of each lane, and the eqb0/b1 pins are converted to smbus ad2/ad3 inputs. table 2 dema, demb 4, 5 io, dema/b controls the level of de-emphasis. the dema/b pins are only active when lvcmos, ensmb is de-asserted (low). each of the 4 a/b channels have the same level float unless controlled by the smbus control registers. when ensmb goes high the smbus (4-levels) registers provide independent control of each lane and the dem pins are converted to smbus scl and sda pins. table 3 tx_dis 6 i, lvcmos ds100br111 high = outa enabled /outb disabled low = outa/b enabled vod_sel 17 i, lvcmos, eq mode and vod select. float high = 10g-kr mode (vod = 1.1v/1.3v) (4-levels) float = (vod = 1.0 v) 20k = (vod = 1.2 v) low = (vod = 700m v) see (2) (3) . see table 4 for additional information. vdd_sel 16 i, internal enables the 3.3v to 2.5v internal regulator pull-up low = 3.3 v operation float = 2.5 v operation (1) lvcmos inputs without the ? float ? conditions must be driven to a logic low or high at all times or operation is not guaranteed. unless the " float " level is desired; 4-level input pins require a minimum 1k resistor to gnd, vdd (in 2.5v mode), or vin (in 3.3v mode).input edge rate for lvcmos/float inputs must be faster than 50 ns from 10 ? 90%. (2) setting vod_sel = high in smbus mode will force the smbus address = b0 ' h (3) ds100br111 outa is limited to 700mv in pin mode. 4 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 pin descriptions (1) (continued) pin name pin number i/o, type pin description mode 18 i, lvcmos controls device mode of operation high = continuous talk float = 10g-kr mode, slow oob 20k ? = esata mode, fast oob, auto low power on 100 us of inactivity. sd stays active. low = sas mode, fast oob status output los 13 o, open indicates loss of signal (default is los on ina). can be modified via smbus drain registers. los threshold input sd_th 14 i, lvcmos, the sd_th pin controls los threshold setting; float assert (mv), deassert (mv) (4-levels) 20k = 160 mv, 100 mv float = 180 mv, 110 mv (default) high = 190 mv, 130 mv low = 210 mv, 150 mv (4) power vdd 21, 22 power power supply pins 2.5v mode connect to 2.5v 3.3v mode do not connect to any supply voltage. should be used to attach external decoupling to device, 100 - 200 nf recommended. see applications information section for additional information. vin 15 power vin = 3.3v +/-10% (input to internal ldo regulator) (5) see applications information section for additional information. gnd dap power ground pad (dap - die attach pad). for additional information table 1 table 5 . (4) using values less than the default level can extend the time required to detect los and are not recommended. (5) must float for 2.5v operation. copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) supply voltage (vdd) -0.5v to +2.75v supply voltage (vin) -0.5v to +4.0v lvcmos input/output voltage -0.5v to +4.0v cml input voltage -0.5v to (vdd+0.5) cml input current -30 to +30 ma junction temperature 125 c storage temperature -40 c to +125 c esd rating hbm, std - jesd22-a114f > 5 kv mm, std - jesd22-a115-a 100 v cdm, std - jesd22-c101-d 1250 v package thermal resistance jc 3.2 c/w ja, no airflow, 4 layer jedec 33.0 c/w for soldering specifications: see product folder at www.national.com www.national.com/ms/ms/ms-soldering.pdf (1) ? absolute maximum ratings ? indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. functional operation of the device and/or non-degradation at the absolute maximum ratings or other conditions beyond those indicated in the recommended operating conditions is not implied. recommended operating conditions (1) min typ max units supply voltage (2.5v mode) 2.375 2.5 2.625 v supply voltage (3.3v mode) 3.0 3.3 3.6 v ambient temperature -40 25 +85 c smbus (sda, scl) 3.6 v (1) the recommended operating conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. absolute maximum numbers are guaranteed for a junction temperature range of -40 c to +125 c. models are validated to maximum operating voltages only. electrical characteristics parameter test conditions min typ max units power supply current idd supply current tx_dis = low, eq = on 50 63 vod_sel = float ( 1000 mv) auto low power mode 12 15 tx_dis = low, mode = 20k ma vid cha and chb = 0.0v vod_sel = float (1000 mv) tx_dis = high (br111) 25 35 lvcmos dc specifications v ih high level input voltage 2.0 vdd v v il low level input voltage gnd 0.7 v v oh high level output i oh = -4.0 ma (1) 2.0 v voltage v ol low level output i ol = 4.0 ma 0.4 v voltage (1) voh only applies to the done# pin; los, scl, and sda are open-drain outputs that have no internal pull-up capability. done# is a full lvcmos output with pull-up and pull-down capability 6 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 electrical characteristics (continued) parameter test conditions min typ max units i in input leakage current vinput = 0v or vdd -15 +15 a vdd_sel = float vinput = 0v or vin -15 +15 vdd_sel = low i in-p input leakage current vinput = 0v or vdd - 0.05v -160 +80 a 4-level input (2) vdd_sel = float vinput = 0v or vin - 0.05v vdd_sel = low los and enable / disable timing t los_off input idle to active see (3) 0.035 s rx_los response time t los_on input active to idle see (3) 0.4 s rx_los response time t off tx disable assert time see (3) 0.005 s tx_dis = high to output off t on tx disable negatetime see (3) 0.150 s tx_dis = low to output on t lp_exit auto low power exit see (3) 150 ns alp to normal operation t lp_enter auto low power enter see (4) 100 us normal operation to auto low power cml receiver inputs v tx source transmit launch default power-up conditions 190 800 1600 mv signal level ensmb = 0 or 1 rl rx-in rx return loss sdd11 @ 4.1 ghz -12 db sdd11 @ 11.1 ghz -8 scd11 @ 11.1 ghz -10 high speed transmitter outputs v od1 output voltage out+ and out- ac coupled 500 650 800 mvp-p differential swing and terminated by 50 ? to gnd vod_sel = low (700 mv setting) de = low v od2 output voltage out+ and out- ac coupled 800 1000 1100 differential swing and terminated by 50 ? to gnd vod_sel = float (1000 mv setting) de = low v od3 output voltage out+ and out- ac coupled 950 1150 1350 differential swing and terminated by 50 ? to gnd vod_sel = 20k (1200 mv setting) de = low v od_de1 de-emphasis levels out+ and out- ac coupled -3 db and terminated by 50 ? to gnd vod_sel = float (1000 mv setting) de = float (2) input is held to a maximum of 50 mv below vdd or vin to simulate the use of a 1k resistor on the input. (3) parameter not tested in production. (4) parameter not tested in production. copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com electrical characteristics (continued) parameter test conditions min typ max units v od_de2 de-emphasis levels out+ and out- ac coupled -6 db and terminated by 50 ? to gnd vod_sel = float (1000 mv setting) de = 20k v od_de3 de-emphasis levels out+ and out- ac coupled -9 db and terminated by 50 ? to gnd vod_sel = float (1000 mv setting) de = high v cm-ac output common-mode ac common mode voltage 4.5 mv (rms) voltage de = 0 db, vod < = 1000 mv v cm-dc output dc common- dc common mode voltage 0 1.1 1.9 v mode voltage v idle tx idle output voltage 30 mv rl tx-diff tx return loss sdd22 @ 4.1 ghz -13 db sdd22 @ 11.1 ghz -9 scc22 @ 2.5 ghz -22 scc22 @ 11.1 ghz -10 delta z m transmitter termination dc, i force = +/- 100 a (5) 2.5 % mismatch t r/f transmitter rise and measurement points at 20% - 38 ps fall time 80% (6) t pd propagation delay measured at 50% crossing 230 ps eq = 00 t ccsk channel to channel t = 25 c, vdd = 2.5v 7 ps skew t ppsk part to part skew t = 25 c, vdd = 2.5v 20 ps t tx-idle-set-to- max time to transition to vin = 1vpp, 10 gbps 6.5 ns idle idle after differential eq = 00, de = 0 signal t tx-idle-to-diff- max time to transition to vin = 1vpp, 10 gbps 3.2 ns data valid differential signal eq = 00, de = 0 after idle t env_distort active oob timing 3.3 ns distortion, input active time vs. output active time output jitter specifications: (7) r j random jitter no media 0.3 ps (rms) source amplitude = 700 mv, d j1 deterministic jitter 0.09 ui prbs15 pattern, 10.3125 gbps vod = default, eq = minimum, de = 0 db equalization d je1 residual deterministic 8 meter 30awg cable on 0.27 ui jitter input 10.3125 gbps source = 700 mv, prbs15 pattern eq = 0f ' h; see figure 16 (5) force +/- 100 ua on output, measure delta v on the output and calculate impedance. mismatch is the percentage difference of outn+ and outn- impedance driving the same logic state. (6) default vod used for testing. de = -1.5 db level used to compensate for fixture attenuation. (7) typical jitter reported is determined by jitter decomposition software on the dsa8200 oscilloscope. 8 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 electrical characteristics (continued) parameter test conditions min typ max units d je2 residual deterministic 30 " 4-mil fr4 on inputs 0.17 ui jitter source = 700 mv, prbs15 10.3125 gbps pattern eq = 16 ' h; see figure 13 de-emphasis d jd1 residual deterministic 10 ? 4 mil stripline fr4 on 0.13 ui jitter outputs 10.3125 gbps source = 700 mv, prbs15 pattern eq = min, vod = 1200 mv, de = 010 ' b see figure 18 copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com electrical characteristics ? serial management bus interface over recommended operating supply and temperature ranges unless other specified. parameter test conditions min typ max units serial bus interface dc specifications: (1) v il data, clock input low voltage 0.8 v v ih data, clock input high voltage 2.1 3.6 v i pullup current through pull-up resistor high power specification 4 ma or current source v dd nominal bus voltage 2.375 3.6 v i leak-bus input leakage per bus segment see (2) -200 +200 a c i capacitance for sda and scl see (2) (3) (4) 10 pf r term external termination resistance pullup v dd = 3.3v, (2) (3) (5) 2000 ? pull to v dd = 2.5v 5% or 3.3v pullup v dd = 2.5v, (2) (3) (5) 1000 ? 10% serial bus interface timing specifications fsmb bus operating frequency ensmb = vdd (slave mode) 400 khz ensmb = float (master mode 280 400 520 khz (1) tbuf bus free time between stop and 1.3 s start condition thd:sta hold time after (repeated) start at i pullup , max condition. after this period, the first 0.6 s clock is generated. tsu:sta repeated start condition setup 0.6 s time tsu:sto stop condition setup time 0.6 s thd:dat data hold time 0 ns tsu:dat data setup time 100 ns t low clock low period 1.3 s t high clock high period see (6) 0.6 50 s t f clock/data fall time see (6) 300 ns t r clock/data rise time see (6) 300 ns t por time in which a device must be see (6) (4) 500 ms operational after power-on reset (1) eeprom interface requires 400 khz capable eeprom device. (2) recommended value. (3) recommended maximum capacitance load per bus segment is 400pf. (4) guaranteed by design and/or characterization. parameter not tested in production. (5) maximum termination voltage should be identical to the device supply voltage. (6) compliant to smbus 2.0 physical layer specification. see system management bus (smbus) specification version 2.0, section 3.1.1 smbus common ac specifications for details. 10 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 timing diagrams figure 2. cml output transition times figure 3. propagation delay timing diagram figure 4. idle timing diagram figure 5. smbus timing parameters copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: ds100br111 sp t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta st sp t su:sto scl sda st
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com functional description the ds100br111 is a high performance circuit capable of delivering excellent performance. careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. refer to the information below and revision 4 of the lvds owner's manual for more detailed information on high speed design tips to address signal integrity design issues. the control pins have been enhanced to have 4 different levels and provide a wider range of control settings. refer to table 1 table 1. 4-level control pin settings pin setting description 0 tie pin to gnd through a 1 k ? resistor r tie pin to ground through 20 k ? resistor float float the pin (no connection) 1 tie pin to vdd through a 1 k ? resistor note 4-level io pins require a 1k resistance to gnd or vdd/vin. it is possible to tie mulitple 4- level io pins together with a single resistor to gnd or vdd/vin. when multiple ios are connected in parallel, the resistance to gnd or vdd/vin should be adjusted to compensate. for 2 pins the optimal resistance is 500 ohms, 3 pins = 330 ohms, and 4 pins = 250 ohms. note for 2.5v mode the control pin logic 1 level is vdd (pins 21 and 22), in 3.3v mode the control pin logic 1 level is defined by vin (pin 15). table 2. equalizer settings eqa1/eqb level eqa0/eqb0 eq ? 8 bits [7:0] db boost at 5 ghz suggested media 1 1 0 0 0000 0000 = 0x00 2.5 fr4 < 5 inch trace 2 0 r 0000 0001 = 0x01 6.5 fr4 5 inch trace 3 0 float 0000 0010 = 0x02 9 fr4 10 inch trace 4 0 1 0000 0011 = 0x03 11.5 fr4 15 inch trace 5 r 0 0000 0111 = 0x07 14 fr4 20 inch trace 6 r r 0001 0101 = 0x15 15 fr4 25 inch trace 7 r float 0000 1011 = 0x0b 17 fr4 25 inch trace 8 r 1 0000 1111 = 0x0f 19 7m 30awg cable 9 float 0 0101 0101 = 0x55 20 fr4 30 inch trace 10 float r 0001 1111 = 0x1f 23 8m 30 awg cable fr4 35 inch trace 11 float float 0010 1111 = 0x2f 25 10m 30 awg cable 12 float 1 0011 1111 = 0x3f 27 10m - 12m, cable 13 1 0 1010 1010 = 0xaa 30 14 1 r 0111 1111 = 0x7f 31 15 1 float 1011 1111 = 0xbf 33 16 1 1 1111 1111 = 0xff 34 12 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 note settings are approximate and will change based on pcb material, trace dimensions, and driver waveform characteristics. table 3. de-emphasis and output voltage settings level vod_sel dema/b smbus register dem level smbus register vod level vod (mv) dem (db) 1 0 0 000 000 700 0 2 0 float 010 000 700 - 3.5 3 0 r 011 000 700 - 6 4 0 1 101 000 700 - 9 5 float 0 000 011 1000 0 6 float float 010 011 1000 - 3.5 7 float r 011 011 1000 - 6 8 float 1 101 011 1000 - 9 9 r 0 000 101 1200 - 0 10 r float 010 101 1200 - 3.5 11 r r 011 101 1200 - 6 12 r 1 101 101 1200 - 9 13 1 0 000 100 1100 0 14 1 float 001 100 1100 - 1.5 15 1 r 001 110 1300 - 1.5 16 1 1 010 110 1300 - 3.5 note the ds100br111 vod for output a is limited to 700 mv in pin mode (ensmb=0). with ensmb = 1 or float, the vod for output a can be adjusted with smbus register 0x23 [4:2] as shown in table 9 . note when vod_sel is in the logic 1 state (1k resistor to vin/vdd) the ds100br111 will support 10g-kr back-channel communication using pin control. note in smbus mode if vod_sel is in the logic 1 state (1k resistor to vin/vdd) the ds100br111 ad0-ad3 pins are internally forced to 0'h table 4. signal detect threshold level smbus reg bit sd_th assert level (typical) de-assert level (typical) [3:2] and [1:0] 0 10 210 mv 150 mv 20k to gnd 01 160 mv 100 mv float (default) 00 180 mv 110 mv 1 11 190 mv 130 mv note: vdd = 2.5v, 25 c, and 010101 pattern at 10 gbps copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com applications information 4-level input configuration guidelines the 4-level input pins utilize a resistor divider to help set the 4 valid levels. there is an internal 30k pull-up and a 60k pull-down connected to the package pin. these resistors, together with the external resistor connection combine to achieve the desired voltage level. using the 1k pull-up, 1k pull-down, no connect, and 20k pull-down provide the optimal voltage levels for each of the four input states. table 5. 4-level input voltage level setting 3.3v mode 2.5v mode 0 01k to gnd 0.1 v 0.08 v r 20k to gnd 0.33 * v in 0.33 * v dd f float 0.67 * v in 0.67 * v dd 1 1k to v dd /v in v in - 0.05v v in - 0.04v ? typical 4-level input thresholds ? level 1 - 2 = 0.2 v in or v dd ? level 2 - 3 = 0.5 v in or v dd ? level 3 - 4 = 0.8 v in or v dd in order to minimize the startup current associated with the integrated 2.5v regulator the 1k pull-up / pull-down resistors are recommended. if several 4 level inputs require the same setting, it is possible to combine two or more 1k resistors into a single lower value resistor. as an example; combining two inputs with a single 500 ? resistor is a good way to save board space. 10g-kr configuration guidelines when configured in "kr mode", using either the vod_sel pin setting or smbus register control, the ds100br111 is designed to operate transparently within a kr backplance channel environment. installing a ds100 repeater within the kr backplane channel splits the total channel attenuation into two parts. ideally the repeater can be placed near the middle of the channel maximizing the signal to noise ratio across the bidirectional interface. in order to maximize the 10g-kr solution space, the 802.3ap specification calls for an optimization of the transmit signal conditioning coefficients based on feedback for the kr receiver. setting the ds100br111 active ctle to compensate for the channel loss from each of the kr transmitters will reduce the transmit and receive equalization settings required on the kr physical layer devices. this central location keeps a larger s/n raito at all points in the channel, extending the available solution space and increasing the overall margin of almost any channel. pcb layout guidelines the cml inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 85 - 100 ? . it is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. the use of vias should be avoided if possible. if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. route the differential signals away from other signals and noise sources on the printed circuit board. see snoa401q an-1187 for additional information on wqfn packages. different transmission line topologies can be used in various combinations to achieve the optimal system performance. impedance discontinuities at vias can be minimized or eliminated by increasing the swell around each hole and providing for a low inductance return current path. when the via structure is associated with thick backplane pcb, further optimization such as back drilling is often used to reduce the detrimental high frequency effects of stubs on the signal path. 14 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 power supply configuration guidelines the ds100br111 can be configured for 2.5v operation or 3.3v operation. the lists below outline required connections for each supply selection. 3.3v mode of operation 1. tie vdd_sel = 0 with 1k resistor to gnd. 2. feed 3.3v supply into vin pin. local 1.0 uf decoupling at vin is recommended. 3. see information on vdd bypass below. 4. sda and scl pins should connect pull-up resistor to vin 5. any 4-level input which requires a connection to "logic 1" should use a 1k resistor to vin 2.5v mode of operation 6. vdd_sel = float 7. vin = float 8. feed 2.5v supply into vdd pins. 9. see information on vdd bypass below. 10. sda and scl pins connect pull-up resistor to vdd for 2.5v uc smbus io 11. sda and scl pins connect pull-up resistor to vdd for 3.3v uc smbus io 12. any 4-level input which requires a connection to "logic 1" should use a 1k resistor to vin note the dap (bottom solder pad) is the gnd connection. power supply bypass two approaches are recommended to ensure that the ds100br111 is provided with an adequate power supply. first, the supply (vdd) and ground (gnd) pins should be connected to power planes routed on adjacent layers of the printed circuit board. the layer thickness of the dielectric should be minimized so that the v dd and gnd planes create a low inductance supply with distributed capacitance. second, careful attention to supply bypassing through the proper use of bypass capacitors is required. a 0.1 f bypass capacitor should be connected to each v dd pin such that the capacitor is placed as close as possible to the device. smaller body size capacitors can help facilitate proper component placement. system management bus (smbus) and configuration registers the system management bus interface is compatible to smbus 2.0 physical layer specification. ensmb must be pulled high to enable smbus mode and allow access to the configuration registers. the ds100br111 has ad[3:0] inputs in smbus mode. these pins are the user set smbus slave address inputs. when pulled low the ad[3:0] = 0000'b, the device default address byte is b0'h. based on the smbus 2.0 specification, this configuration results in a 7-bit slave address of 1011000'b. the lsb is set to 0'b (for a write), thus the 8-bit value is 1011 0000'b or b0'h. the device address byte can be set with the use of the ad[3:0] inputs. shown in the form of an expression: slave address [7:4] = the ds100br111 hardware address (1011'b) + address pin ad[3] slave address [3:1] = address pins ad[2:0] slave address [0] = 0'b for a write or 1'b for a read slave address examples: ? ad[3:0] = 0001'b, the device slave address byte is b2'h ? slave address [7:4] = 1011'b + 0'b = 1011'b or b'h ? slave address [3:1] = 001'b ? slave address [0] = 0'b for a write ? ad[3:0] = 0010'b, the device slave address byte is b4'h copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com ? slave address [7:4] = 1011'b + 0'b = 1011'b or b'h ? slave address [3:1] = 010'b ? slave address [0] = 0'b for a write ? ad[3:0] = 0100'b, the device slave address byte is b8'h ? slave address [7:4] = 1011'b + 0'b = 1011'b or b'h ? slave address [3:1] = 100'b ? slave address [0] = 0'b for a write ? ad[3:0] = 1000'b, the device slave address byte is c0'h ? slave address [7:4] = 1011'b + 1'b = 1100'b or c'h ? slave address [3:1] = 000'b ? slave address [0] = 0'b for a write 16 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 transfer of data via the smbus during normal operation the data on sda must be stable during the time when scl is high. there are three unique states for the smbus: start: a high-to-low transition on sda while scl is high indicates a message start condition. stop: a low-to-high transition on sda while scl is high indicates a message stop condition. idle: if scl and sda are both high for a time exceeding t buf from the last detected stop condition or if they are high for a total exceeding the maximum specification for t high then the bus will transfer to the idle state. smbus transactions the device supports write and read transactions. see table 9 for register address, type (read/write, read only), default value and function information. writing a register to write a register, the following protocol is used (see smbus 2.0 specification). 1. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 2. the device (slave) drives the ack bit ( ? 0 ? ). 3. the host drives the 8-bit register address. 4. the device drives an ack bit ( ? 0 ? ). 5. the host drive the 8-bit data byte. 6. the device drives an ack bit ( ? 0 ? ). 7. the host drives a stop condition. the write transaction is completed, the bus goes idle and communication with other smbus devices may now occur. reading a register to read a register, the following protocol is used (see smbus 2.0 specification). 1. the host drives a start condition, the 7-bit smbus address, and a ? 0 ? indicating a write. 2. the device (slave) drives the ack bit ( ? 0 ? ). 3. the host drives the 8-bit register address. 4. the device drives an ack bit ( ? 0 ? ). 5. the host drives a start condition. 6. the host drives the 7-bit smbus address, and a ? 1 ? indicating a read. 7. the device drives an ack bit ? 0 ? . 8. the device drives the 8-bit data value (register contents). 9. the host drives a nack bit ? 1 ? indicating end of the read transfer. 10. the host drives a stop condition. the read transaction is completed, the bus goes idle and communication with other smbus devices may now occur. please see table 9 for more information. figure 6. typical smbus write operation copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: ds100br111 p a 2 a 1 a 0 0 s + a3 slave address a ck 01234567 device id register address a ck s a 2 a 1 a 0 1 01234567 a ck slave address a ck data + a3 device id
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com eeprom modes in ds100br111 devices the ds100br111 supports reading directly from an external eeprom device by implementing smbus master mode. when using the smbus master mode, the ds100 will read directly from specific location in the external eeprom. when designing a system for using the external eeprom, the user needs to follow these specific guidelines. ? set the ds100br111 into smbus master mode ? float ensmb (pin 3) ? the external eeprom device must support 400 khz operation ? the external eeprom device address byte must be 0xa0'h ? set the ad[3:0] inputs for smbus address byte. when the ad[3:0] = 0000'b, the device address byte is b0'h. ? based on the smbus 2.0 specification, a device can have a 7-bit slave address of 1010 000'b. the lsb is set to 0'b (for a write). the bit mapping for smbus is listed below: ? [7:5] = reserved bits from the smbus specification ? [4:1] = usable smbus address bits ? [0] = write bit ? the ds100br111 devices have ad[3:0] inputs in smbus mode (pins 1, 2, 9, 10). these pins set smbus slave address. when the ad[3:0] = 0001'b, the device address byte is b2'h. ? [7:5] = default to 3b'101 ? [4:1] = address of 4'b0001 ? [0] = write bit, 1'b0 ? the device address can be set with the use of the ad[3:0] input up to 16 different addresses. use the example below to set each of the smbus addresses. ? ad[3:0] = 0001'b, the device address byte is b2'h ? ad[3:0] = 0010'b, the device address byte is b4'h ? ad[3:0] = 0011'b, the device address byte is b6'h ? ad[3:0] = 0100'b, the device address byte is b8'h ? the master implementation in the ds100br111 supports multiple devices reading from 1 eeprom. when tying multiple devices to the sda and scl pins, use these guidelines: ? use adjacent smbus addresses for the 4 devices ? use a pull-up resistor on sda; value = 4.7k ? ? use a pull-up resistor on scl: value = 4.7k ? ? daisy-chain readen# (pin 17) and done# (pin18) from one device to the next device in the sequence 1. tie readen# of the 1st device in the chain (u1) to gnd 2. tie done# of u1 to readen# of u2 3. tie done# of u2 to readen# of u3 4. tie done# of u3 to readen# of u4 5. optional: tie done# of u4 to a led to show each of the devices have been loaded successfully master eeprom mode in the ds100br111 below is an example of a 2 kbits (256 x 8-bit) eeprom in hex format for the ds100br111 device. the first 3 bytes of the eeprom always contain a header common and necessary to control initialization of all devices connected to the i2c bus. crc enable flag to enable/disable crc checking. there is a map bit to flag the presence of an address map that specifies the configuration data start in the eeprom. if the map bit is not present the configuration data start address is derived from the ds100br111 address and the configuration data size. a bit to indicate an eeprom size > 256 bytes is necessary to properly address the eeprom. there are 37 bytes of data size for each ds100br111 device. 18 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 figure 7. typical eeprom data set the crc-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the ds100br111 or 40 bytes in total. the result of this calculation is placed immediately after the ds100br111 data in the eeprom which ends with "5454". the crc-8 in the ds100br111 uses a polynomial = x 8 + x 2 + x + 1 in smbus master mode the ds100br111 reads its initial configuration from an external eeprom upon power- up. some of the pins of the ds100br111 perform the same functions in smbus master and smbus slave mode. once the ds100br111 has finished reading its initial configuration from the external eeprom in smbus master mode it reverts to smbus slave mode and can be further configured by an external controller over the smbus. the connection to an external smbus master is optional and can be omitted for applications were additional security is desirable. there are two pins that provide unique functions in smbus master mode. ? done# ? readen# when the ds100br111 is powered up in smbus master mode, it reads its configuration from the external eeprom when the readen# pin goes low. when the ds100br111 is finished reading its configuration from the external eeprom, it drives the done# pin low. in applications where there is more than one ds100br111 on the same smbus, bus contention can result if more than one ds100br111 tries to take control of the smbus at the same time. the readen# and done# pins prevent this bus contention. the system should be designed so that the readen# pin from one ds100br111 in the system is driven low on power-up. this ds100br111 will take command of the smbus on power-up and will read its initial configuration from the external eeprom. when it is finished reading its configuration, it will drive the done# pin low. this pin should be connected to the readen# pin of another ds100br111. when this ds100br111 senses its readen# pin driven low, it will take command of the smbus and read its initial configuration from the external eeprom, after which it will set its done# pin low. by connecting the done# pin of each ds100br111 to the readen# pin of the next ds100br111, each ds100br111 can read its initial configuration from the eeprom without causing bus contention. copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: ds100br111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 : 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 4 0 7 0 0 2 f e d 4 0 0 2 f e d 4 0 0 2 f c 4 : 1 0 0 0 1 0 0 0 a d 4 0 0 2 f a d 4 0 0 0 0 5 f 5 6 8 0 0 5 f 5 a 8 0 0 5 f 5 a e 9 : 1 0 0 0 2 0 0 0 8 0 0 5 f 5 a 8 0 0 0 0 5 4 5 4 f 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 8 : 1 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 : 1 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 : 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 : 1 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 : 1 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 : 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 : 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 : 1 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 : 1 0 0 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 : 1 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 : 1 0 0 0 d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 : 1 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 : 1 0 0 0 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 1 f f crc-8 based on 40 bytes of data in this shaded area insert the crc value here crc polynomial = 0x07 max eeprom burst = 32
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com figure 8. typical multi-device eeprom connection diagram 20 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen# done# sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen# done# sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 outa+ outa- outb+ vdd_sel vin 18 inb+ inb- 17 14 13 16 los readen# done# sd_th ina+ ina- outb- smbus and control 15 vdd 24 23 22 21 20 19 11 12 8 10 9 7 ad2 ensmb 1 2 5 63 scl ad3 sda 4 vdd tx_dis ad1 ad0 sda scl ad0 ad1 ad2 gnd gnd gnd one or both of these lines should float for eeprom larger than 256 bytes. eeprom sda scl from external smbus master 3.3v float float float note: set ad[3:0] of each ds100br111 to unique smbus address. gnd
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 6. multi-device eeprom register map overview addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 crc en address map eeprom > reserved count[3] count[2] count[1] count[0] 256 bytes header 1 reserved reserved reserved reserved reserved reserved reserved reserved 2 ee burst[7] ee burst[6] ee burst[5] ee burst[4] ee burst[3] ee burst[2] ee burst[1] ee burst[0] device 0 3 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 4 ee ad0 [7] ee ad0 [6] ee ad0 [5] ee ad0 [4] ee ad0 [3] ee ad0 [2] ee ad0 [1] ee ad0 [0] device 1 5 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 6 ee ad1 [7] ee ad1 [6] ee ad1 [5] ee ad1 [4] ee ad1 [3] ee ad1 [2] ee ad1 [1] ee ad1 [0] device 2 7 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 8 ee ad2 [7] ee ad2 [6] ee ad2 [5] ee ad2 [4] ee ad2 [3] ee ad2 [2] ee ad2 [1] ee ad2 [0] device 3 9 crc[7] crc[6] crc[5] crc[4] crc[3] crc[2] crc[1] crc[0] info 10 ee ad3 [7] ee ad3 [6] ee ad3 [5] ee ad3 [4] ee ad3 [3] ee ad3 [2] ee ad3 [1] ee ad3 [0] device 0 11 res res res res res res res res addr 3 device 0 12 res res pdwn inp pdwn osc res esata cha esata chb ovrd tx_dis addr 4 device 0 46 res res res res res res res res addr 38 device 0 47 dres res res res res res res res addr 39 device 1 48 res res res res res res res res addr 3 device 1 49 res res pdwn inp pdwn osc res esata cha esata chb ovrd tx_dis addr 4 device 1 83 res res res res res res res res addr 38 device 1 84 res res res res res res res res addr 39 device 2 85 res res res res res res res res addr 3 device 2 86 res res pdwn inp pdwn osc res esata cha esata chb ovrd tx_dis addr 4 device 2 120 res res res res res res res res addr 38 device 2 121 res res res res res res res res addr 39 device 3 122 res res res res res res res res addr 3 device 3 123 res res pdwn inp pdwn osc res esata cha esata chb ovrd tx_dis addr 4 device 3 157 res res res res res res res res addr 38 device 3 158 res res res res res res res res addr 39 ? crc en = 1; address map = 1 ? eeprom > 256 bytes = 0 ? count[3:0] = 0011'b ? note: multiple ds100br111 devices may point at the same address space if they have identical programming values. copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com table 7. single eeprom header + register map with default value eeprom bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address byte 0 crc en address map eeprom > res count[3] count[2] count[1] count[0] description present 256 bytes value 0 0 0 0 0 0 0 0 description 1 res res res res res res res res value 0 0 0 0 0 0 0 0 2 max max max max max max max max description eeprom eeprom eeprom eeprom eeprom eeprom eeprom eeprom burst size[7] burst size[6] burst size[5] burst size[4] burst size[3] burst size[2] burst size[1] burst size[0] value 0 0 0 0 0 0 0 0 description 3 reserved reserved reserved reserved reserved reserved reserved reserved register 0x01 [7] 0x01 [6] 0x01 [5] 0x01 [4] 0x01 [3] 0x01 [2] 0x01 [1] 0x01 [0] value 0 0 0 0 0 0 0 0 description 4 ovrd_los los_value pdwn inp pwdn osc reserved esata esata ovrd tx_dis enable a enable b register 0x02 [5] 0x02 [4] 0x02 [3] 0x02 [2] 0x02 [0] 0x04 [7] 0x04 [6] 0x04 [5] value 0 0 0 0 0 0 0 0 description 5 tx_dis cha tx_dis chb reserved eq stage 4 eq stage 4 reserved overide reserved chb cha idle_th register 0x04 [4] 0x04 [3] 0x04 [2] 0x04 [1] 0x04 [0] 0x06 [4] 0x08 [6] 0x08 [5] value 0 0 0 0 0 1 0 0 description 6 ovrd_idle reserved ovrd_out reserved reserved reserved reserved reserved mode register 0x08 [4] 0x08 [3] 0x08 [2] 0x08 [1] 0x08 [0] 0x0b [6] 0x0b [5] 0x0b [4] value 0 0 0 0 0 1 1 1 description 7 reserved reserved reserved reserved idle auto a idle sel a reserved reserved register 0x0b [3] 0x0b [2] 0x0b [1] 0x0b [0] 0x0e [5] 0x0e [4] 0x0e [3] 0x0e [2] value 0 0 0 0 0 0 0 0 description 8 cha eq[7] cha eq[6] cha eq[5] cha eq[4] cha eq[3] cha eq[2] cha eq[1] cha eq[0] register 0x0f [7] 0x0f [6] 0x0f [5] 0x0f [4] 0x0f [3] 0x0f [2] 0x0f [1] 0x0f [0] value 0 0 1 0 1 1 1 1 description 9 a sel scp a out mode reserved reserved reserved reserved reserved reserved register 0x10 [7] 0x10 [6] 0x10 [5] 0x10 [4] 0x10 [3] 0x10 [2] 0x10 [1] 0x10 [0] value 1 1 1 0 1 1 0 1 description 10 dema[2] dema[1] dema[0] cha slow idle tha[1] idle tha[0] idle thd[1] idle thd[0] register 0x11 [2] 0x11 [1] 0x11 [0] 0x12 [7] 0x12 [3] 0x12 [2] 0x12 [1] 0x12 [0] value 0 1 0 0 0 0 0 0 description 11 idle auto b idle sel b reserved reserved chb eq[7] chb eq[6] chb eq[5] chb eq[4] register 0x15 [5] 0x15 [4] 0x15 [3] 0x15 [2] 0x16 [7] 0x16 [6] 0x16 [5] 0x16 [4] value 0 0 0 0 0 0 1 0 description 12 chb eq[3] chb eq[2] chb eq[1] chb eq[0] b sel scp b out mode reserved reserved register 0x16 [3] 0x16 [2] 0x16 [1] 0x16 [0] 0x17 [7] 0x17 [6] 0x17 [5] 0x17 [4] value 1 1 1 1 1 1 1 0 description 13 reserved reserved reserved reserved chb dem[2] chb dem[1] chb dem[0] chb slow register 0x17 [3] 0x17 [2] 0x17 [1] 0x17 [1] 0x18 [2] 0x18 [1] 0x18 [0] 0x19 [7] value 1 1 0 1 0 1 0 0 description 14 idle tha[1] idle tha[0] idle thd[1] idle thd[0] reserved reserved reserved reserved register 0x19 [3] 0x19 [2] 0x19 [1] 0x19 [0] value 0 0 0 0 0 0 0 0 22 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 7. single eeprom header + register map with default value (continued) eeprom bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address byte description 15 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 1 0 1 1 1 1 description 16 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 0 1 0 1 1 0 1 description 17 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 0 0 0 0 0 description 18 reserved cha vod[2] cha vod[1] cha vod[0] reserved reserved reserved reserved register 0x23 [4] 0x23 [3] 0x23 [2] value 0 0 0 0 0 0 1 0 description 19 reserved reserved reserved reserved reserved reserved reserved reserved register 0x25 [4] value 1 1 1 1 1 0 1 0 description 20 reserved reserved reserved reserved reserved reserved reserved reserved register 0x25 [3] 0x25 [2] value 1 1 0 1 0 1 0 0 description 21 reserved reserved reserved reserved ovrd fst idle en hi idle th en hi idle th en fst idle a a b register 0x28 [6] 0x28 [5] 0x28 [4] 0x28 [3] value 0 0 0 0 0 0 0 0 description 22 en fst idle b sd mgain a sd mgain b reserved reserved reserved reserved reserved register 0x28 [2] 0x28 [1] 0x28 [0] value 0 0 0 0 0 0 0 0 description 23 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 1 1 1 1 1 description 24 reserved reserved reserved reserved chb vod[2] chb vod[1] chb vod[0] reserved register 0x2d [4] 0x2d 3] 0x2d [2] value 0 1 0 1 0 1 1 0 description 25 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 0 0 0 0 0 0 0 description 26 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 0 0 0 1 0 1 description 27 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 1 1 1 0 1 0 1 description 28 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 0 1 0 1 0 0 0 description 29 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 0 0 0 0 0 0 copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com table 7. single eeprom header + register map with default value (continued) eeprom bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address byte description 30 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 1 1 1 1 1 description 31 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 1 1 0 1 0 description 32 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 0 0 0 0 0 0 0 description 33 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 0 0 0 1 0 1 description 34 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 1 1 1 0 1 0 1 description 35 reserved reserved reserved reserved reserved reserved reserved reserved register value 1 0 1 0 1 0 0 0 description 36 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 0 0 0 0 0 0 description 37 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 0 0 0 0 0 0 0 description 38 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 1 0 1 0 0 description 39 reserved reserved reserved reserved reserved reserved reserved reserved register value 0 1 0 1 0 1 0 0 below is an example of a 2 kbits (256 x 8-bit) eeprom register dump in hex format for a multi-device ds100br111 application. 24 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 8. multi ds100br111 eeprom data eeprom eeprom address (hex) comments address data 0 00 0x43 crc_en = 0, address map = 1, device count = 3 (devices 0, 1, 2, and 3) 1 01 0x00 2 02 0x08 eeprom burst size 3 03 0x00 crc not used 4 04 0x0b device 0 address location 5 05 0x00 crc not used 6 06 0x30 device 1 address location 7 07 0x00 crc not used 8 08 0x30 device 2 address location 9 09 0x00 crc not used 10 0a 0x0b device 3 address location 11 0b 0x00 begin device 0 and device 3 - address offset 3 12 0c 0x00 13 0d 0x04 14 0e 0x07 15 0f 0x00 16 10 0x2f default eq cha 17 11 0xed 18 12 0x40 19 13 0x02 default eq chb 20 14 0xfe default eq chb 21 15 0xd4 22 16 0x00 23 17 0x2f 24 18 0xad 25 19 0x40 26 1a 0x02 br111 cha vod = 700 mv 27 1b 0xfa 28 1c 0xd4 29 1d 0x01 30 1e 0x80 31 1f 0x5f 32 20 0x56 br111 chb vod = 1000 mv 33 21 0x80 34 22 0x05 35 23 0xf5 36 24 0xa8 37 25 0x00 38 26 0x5f 39 27 0x5a 40 28 0x80 41 29 0x05 42 2a 0xf5 43 2b 0xa8 44 2c 0x00 45 2d 0x00 46 2e 0x54 copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com table 8. multi ds100br111 eeprom data (continued) eeprom eeprom address (hex) comments address data 47 2f 0x54 end device 0 and device 3 - address offset 39 48 30 0x00 begin device 1 and device 2 - address offset 3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x2f default eq cha 54 36 0xed 55 37 0x40 56 38 0x02 default eq chb 57 39 0xfe default eq chb 58 3a 0xd4 59 3b 0x00 60 3c 0x2f 61 3d 0xad 62 3e 0x40 63 3f 0x02 br111 cha vod = 700 mv 64 40 0xfa 65 41 0xd4 66 42 0x01 67 43 0x80 68 44 0x5f 69 45 0x56 br111 chb vod = 1000 mv 70 46 0x80 71 47 0x05 72 48 0xf5 73 49 0xa8 74 4a 0x00 75 4b 0x5f 76 4c 0x5a 77 4d 0x80 78 4e 0x05 79 4f 0xf5 80 50 0xa8 81 51 0x00 82 52 0x00 83 53 0x54 84 54 0x54 end device 1 and device 2 - address offset 39 26 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 9. smbus register map register eeprom address bits field type default description name reg bit 0x00 device id 7 reserved r/w 0x00 set bit to 0 6:3 i2c address [3:0] r [6:3] smbus strap observation 2 eeprom reading r 1: eeprom loading done 0: eeprom done loading 1 reserved rwsc set bit to 0 0 reserved rwsc set bit to 0 0x01 control 1 7:6 idle control r/w 0x00 yes control [7]: continuous talk enable (channel a) [6]: continuous talk enable (channel b) 5:3 reserved r/w set bits to 0 2 los select r/w los monitor selection 1: use los from ch b 0: use los from ch a 1:0 reserved r/w set bits to 00'b 0x02 control 2 7 reserved r/w 0x00 set bit to 0 6 reserved set bit to 0 5 los override yes los pin override enable (1); use normal signal detection (0) 4 los override value yes 1: normal operation 0: output los 3 pwdn inputs yes 1: pwdn 0: normal operation 2 pwdn oscillator yes 1 reserved 0 reserved yes set bit to 0 0x04 control 3 7:6 esata mode r/w 0x00 yes [7] channel a (1) enable [6] channel b (1) 5 tx_dis override 1: override use reg 0x04[4:3] enable 0: normal operation - uses pin 4 tx_dis value 1: tx disabled channel a 0: tx enabled 3 tx_dis value channel b 2 reserved set bit to 0 1:0 eq control [1]: channel b - eq stage 4 on/off [0]: channel a - eq stage 4 on/off 0x05 crc 1 7:0 crc[7:0] r/w 0x00 slave mode crc bits 0x06 crc 2 7 disable eeprom r/w 0x10 disable master mode eeprom configuration cfg 6:5 reserved set bits to 0 4 reserved yes set bit to 1 3 crc slave mode [1]: crc disable (no crc check) disable [0]: crc check enable note: with crc check disabled register updates take immediate effect on high speed data path. with crc check enabled register updates will not take effect until correct crc value is loaded 2:1 reserved set bits to 0 0 crc enable slave crc trigger copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com table 9. smbus register map (continued) register eeprom address bits field type default description name reg bit 0x07 digital reset 7 reserved r/w 0x01 set bit to 0 and control 6 reset regs self clearing reset for registers. writing a [1] will return register settings to default values. 5 reset smbus self clearing reset for smbus master state master machine 4:0 reserved set bits to '0001b 0x08 pin override 7 reserved r/w 0x00 set bit to 0 6 override idle yes [1]: override by channel - see reg 0x13 and threshold 0x19 [0]: sd_th pin control 5 reserved yes set bit to 0 4 override idle yes [1]: force idle by channel - see reg 0x0e and 0x15 [0]: normal operation 3 reserved yes set bit to 0 2 override out mode [1]: enable output mode control for individual outputs. see register locations 0x10[6] and 0x17[6]. [0]: disable - outputs are kept in the normal mode of operation allowing vod and de adjustments. 1 override dem yes 0 reserved yes set bit to 0 0x0c ch a 7 reserved r/w 0x00 set bit to 0 analog 6 reserved set bit to 0 override 1 5 reserved set bit to 0 4 reserved set bit to 0 3:0 reserved set bits to 0000'b. 0x0d ch a 7:0 reserved r/w 0x00 set bits to 00'h. reserved 0x0e ch a 7:6 reserved r/w 0x00 set bits to 00'b. idle control 5 idle auto yes auto idle value when override bit is set (reg 0x08 [4] = 1) 4 idle select yes force idle value when override bit is set (reg 0x08 [4] = 1) 3 reserved yes set bit to 0. 2:0 reserved set bits to 0. 0x0f ch a 7:0 boost [7:0] r/w 0x2f yes eq boost default to 24 db eq setting see table 2 for information 0x10 ch a 7 sel_scp r/w 0xed yes [1]: short circuit protection on control 1 [0]: short circuit protection off 6 output mode yes [1]: normal operation [0]: 10g-kr operation 5:3 reserved yes set bits to = 101'b 2:0 reserved yes set bits to = 101'b 28 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 9. smbus register map (continued) register eeprom address bits field type default description name reg bit 0x11 ch a 7:5 reserved r 0x82 set bits to = 100'b control 2 4 reserved r/w set bit to 0 3 reserved set bit to 0 2:0 dem [2:0] yes de-emphasis (default = -3.5 db) 000'b = -0.0 db 001'b = -1.5 db 010'b = -3.5 db 011'b = -6.0 db 100'b = -8.0 db 101'b = -9.0 db 110'b = -10.5 db 111'b = -12.0 db 0x12 ch a 7 slow oob r/w 0x00 yes slow oob enable (1); disable (0) idle 6:4 reserved set bits to 000'b. threshold 3:2 idle tha[1:0] yes assert thresholds use only if register 0x08 [6] = 1 00 = 180 mv (default) 01 = 160 mv 10 = 210 mv 11= 190 mv 1:0 idle thd[1:0] yes de-assert thresholds use only if register 0x08 [6] = 1 00 = 110 mv (default) 01 = 100 mv 10 = 150 mv 11= 130 mv 0x13 ch b 7 reserved r/w 0x00 set bit to 0 analog 6 reserved set bit to 0 override 1 5 reserved set bit to 0 4 reserved set bit to 0 3:0 reserved set bits to 0000'b. 0x14 ch b 7:0 reserved r/w 0x00 set bits to 00'h. reserved 0x15 ch b 7:6 reserved r/w 0x00 set bits to 00'b idle control 5 idle auto yes auto idle value when override bit is set (reg 0x08 [4] = 1) 4 idle select yes force idle value when override bit is set (reg 0x08 [4] = 1) 3:2 reserved yes set bits to 00'b. 1:0 reserved set bits to 00'b. 0x16 ch b 7:0 boost [7:0] r/w 0x2f yes eq boost default to 24 db eq setting see table 2 for information 0x17 ch b 7 sel_scp r/w 0xed yes 1 = short circuit protection on control 1 0 = short circuit protection off 6 output mode yes [1]: normal operation [0]: 10g-kr operation 5:3 reserved yes set bits to = 101'b 2:0 reserved set bits to = 101'b copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com table 9. smbus register map (continued) register eeprom address bits field type default description name reg bit 0x18 ch b 7:5 reserved r 0x82 set bits to = 100'b control 2 4 reserved r/w set bit to 0 3 reserved set bit to 0 2:0 dem [2:0] yes de-emphasis (default = -3.5 db) 000'b = -0.0 db 001'b = -1.5 db 010'b = -3.5 db 011'b = -6.0 db 100'b = -8.0 db 101'b = -9.0 db 110'b = -10.5 db 111'b = -12.0 db 0x19 ch b 7 slow oob r/w 0x00 yes slow oob enable (1); disable (0) idle 6:4 reserved set bits to 000'b. threshold 3:2 idle tha[1:0] yes assert thresholds use only if register 0x08 [6] = 1 00 = 180 mv (default) 01 = 160 mv 10 = 210 mv 11= 190 mv 1:0 idle thd[1:0] yes de-assert thresholds use only if register 0x08 [6] = 1 00 = 110 mv (default) 01 = 100 mv 10 = 150 mv 11= 130 mv 0x23 ch a vod 7:6 reserved r/w 0x00 set bits to 00'b. control 4:2 vod_ch0[2:0] yes ds100br111 vod controls for ch a (default = 000'b) 000'b = 700 mv 001'b = 800 mv 010'b = 900 mv 011'b = 1000 mv 100'b = 1100 mv 101'b = 1200 mv 110'b = 1300 mv 1:0 reserved set bits to 00'b. 0x25 reserved 7:5 reserved r/w 0xad set bits to 101'b. 4:2 reserved yes set bits to 011'b. 1:0 reserved set bits to 01'b. 0x28 idle control 7 reserved r/w 0x00 6 override fast idle yes 5:4 en_high_idle_th[1: yes enable high sd thresholds 0] [5]: ch a [4]: ch b 3:2 en_fast_idle[1:0] yes enable fast idle [3]: ch a [2]: ch b 1:0 reserved yes set bits to 00'b. 30 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 table 9. smbus register map (continued) register eeprom address bits field type default description name reg bit 0x2d ch b vod 7:5 reserved r/w 0xad set bits to 101'b. control 4:2 vod_ch0[2:0] yes vod controls for ch b (default = 011'b) 000'b = 700 mv 001'b = 800 mv 010'b = 900 mv 011'b = 1000 mv 100'b = 1100 mv 101'b = 1200 mv 110'b = 1300 mv 1:0 reserved set bits to = 01'b 0x51 device 7:5 version[2:0] r 0x67 read bits = 011'b information 4:0 device id[4:0] br111 = 0 0111'b copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 31 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com typical dc performance characteristics the following data was collected at 25 c figure 9. supply current vs. output voltage setting figure 10. supply current vs. supply voltage figure 11. output voltage vs. output voltage setting 32 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111 700 800 900 1000 1100 1200 1300 0 10 20 30 40 50 60 70 80 90 100 supply current (ma) output voltage (mv) 3.3v mode 2.5v mode 0 1 2 3 4 5 6 7 500 600 700 800 900 1000 1100 1200 1300 1400 1500 output voltage (mv) vod setting 2.0 2.2 2.4 2.6 2.8 3.0 40 44 48 52 56 60 supply current (ma) supply voltage (v) vod = 700 mv temp = 25c 2.5v mode
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 typical ac performance characteristics no media: device random jitter (rj) deterministic jitter (dj) dj component breakdown total jitter (tj @ 1e- 12) ds100br111 @ 280 fs 9.8 ps ddj = 7.6 ps 13.7 ps 10.3125 gbps dcd = 2.1 ps ddpws = 5.4 ps pj = 0.25 ps figure 12. no media; d3186 driving device directly copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 33 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com equalization results: the following lab setups were used to collect typical performance data on fr4 and cable media figure 13. equalization test setup for fr4 figure 14. equalization performance with 10 " of 4 mil fr4 using eq settting 0x01 figure 15. equalization performance with 30 " of 4 mil fr4 using eq settting 0x16 34 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111 d3186 dsa8200 20 ghz bandwidth br111 evk signal generator fr4 100 ohm differential stripline oscilloscope
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 cable transmit and receive results: figure 16. equalization test setup for cables figure 17. 8m 30awg cable performance with 700mv launch vod and rx eq setting 0x0f copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 35 product folder links: ds100br111 d3186 dsa8200 20 ghz bandwidth cable br111 evk oscilloscope signal generator cable adapter cable adapter
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com de-emphasis results: figure 18. de-emphasis test setup figure 19. de-emphasis performance with 5 " of 4 mil fr4 using de settting 0x01 figure 20. 5 " of 4 mil fr4 without de-emphasis 36 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111 d3186 br111 evk dsa8200 20 ghz bandwidth oscilloscope signal generator fr4 100 ohm differential impedance
ds100br111 www.ti.com snls338e ? january 2011 ? revised february 2013 figure 21. de-emphasis performance with 10 " of 4 mil fr4 using de settting 0x02 figure 22. 10 " of 4 mil fr4 without de-emphasis copyright ? 2011 ? 2013, texas instruments incorporated submit documentation feedback 37 product folder links: ds100br111
ds100br111 snls338e ? january 2011 ? revised february 2013 www.ti.com revision history changes from revision d (february 2013) to revision e page ? changed layout of national data sheet to ti format .......................................................................................................... 37 38 submit documentation feedback copyright ? 2011 ? 2013, texas instruments incorporated product folder links: ds100br111
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ds100br111sq/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 br111 ds100br111sqe/nopb active wqfn rtw 24 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 br111 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ds100br111sq/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 ds100br111sqe/nopb wqfn rtw 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 package materials information www.ti.com 14-mar-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ds100br111sq/nopb wqfn rtw 24 1000 213.0 191.0 55.0 ds100br111sqe/nopb wqfn rtw 24 250 213.0 191.0 55.0 package materials information www.ti.com 14-mar-2013 pack materials-page 2
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